I’ve been busy.  Here is the latest batch of designs that have been sent out for fab.  Some are simple, some more complicated, and some are updates of earlier designs.  KiCad and JLCPCB sure make this stuff easy!

Look for these designs to show up on the Turn Island Systems website.

RX-888 External Clock Interface Kit:

This is a fairly simple kit that provides termination, appropriate attenuation, and DC isolation for the external clock interface to the RX888 SDR.  This includes the interface card, and a replacement back-panel for the RX888.  The complete kit will also include a short U.FL jumper cable and a piece of thermal foam gasket that is used to reduce the RX888 internal temperature rise.

That SMA plug shown on the right side of the board is not present when this board is installed inside the RX888, but can be soldered on when the board is used externally.

Updated Clock Distribution Buffer:

The existing five-output clock buffer has proven quite useful for distributing reference clocks in multiple-SDR receiver systems.  Since I am running out of that unit, I have sent this upgraded design for fabrication and assembly.  This new design now provides six outputs, each with jumper-selectable AC/DC coupling on both the signal and ground connections.  The AC coupling won’t make any difference if you have RF ground-loop issues, but can really help with DC/power supply ground issues (as we often see with USB-powered devices).  This new board also provides a power/clock indicator LED.

AC-Coupled SMA Adaptor:

This tiny board provides capacitor-coupling for both signal and ground.  While it’s simple, it can be very useful when dealing with grounding issues.  Note that the commonly-available DC-block adaptors only block the signal pin, and still leave the grounds connected.

Filter/Preamp V2:

This is my second try with the filter-preamp.  I have rearranged the low-pass filter to (I hope) reduce blow-by, and have upgraded the amplifier to use a Minicircuits MAV-11BSM+ device.  This should improve the intermodulation distortion and provide a good noise figure.  I have also moved the amplifier to the output of the low-pass filter, to reduce potential out-of-band overload issues.

The SMA jack and plug positions provide the option for the in-line jack/plug and right-angle jack/jack configurations.

I may eventually replace the MAV-11 amplifier with a high-speed current-feedback amplifier, which should result in excellent distortion numbers,  reasonable noise figure, and lower power consumption.  But for now the current design should be a good performer, and I want to verify the performance of the new filter arrangement.

In my last entry I described a feature and option-laden filter/preamp board, comparing it to a Swiss Army Knife.  Great, but sometimes you just want a can opener…

After some serious discussion about how such a design would be used, and the typical requirements, I’ve decided that a major simplification is in order.  (And, of course, a new feature)

The consensus was that there was no need for bypassable filters, so the stages are now:

• 18 dB shelf filter (-9 dB @ 6 MHz)
• 17 dB preamp
• 30 MHz elliptic low-pass filter (or 60 MHz as a different assembly)

This board is powered by an external +12V DC supply, and draws about 20 mA.  There is an active-filter stage that should clean up most supply noise.  The new feature is simple low-loss reverse-polarity protection for the power input.

Here is the (simulated) gain of this unit:

And the schematic:

Actually, the two filters can be bypassed at assembly time as a load-option.  Perhaps this will let this board also be used as an amplifier-only design.

I have sent this design out for PCB fabrication and ordered the components — I can’t wait to see how it all comes together!

Transmitters and computers often don’t get along.  Cables going to computers, routers, ethernet switches, USB hubs (and anything else with wires) can pick up RF and disrupt operations.  This RF can be coming from your near-by antenna, from leaky coax, or from the transmitter itself.  Usually when this happens the easiest fix is to add ferrite chokes to the cables.  Sometimes it takes several chokes on a cable.  You will end up experimenting.

The ferrites you will find on eBay (etc.) are probably designed for VHF signal suppression. They will work after a fashion on the HF bands, but you will have better results if you use ferrites made from a material optimized for HF frequencies. Cores using “31” material from the “Fair-Rite” company are excellent performers. These come in all shapes and sizes, but the clamp-on core shown below has proven to be quite useful.

https://www.fair-rite.com/product/round-cable-snap-its-431164181/

Fair-Rite Products Corp
Part Number: 0431164181
31 ROUND CABLE CORE ASSEMBLY
Lower & Broadband Frequencies 1-300 MHz (31 material)

You can buy these from Mouser:
http://www.mouser.com/ProductDetail/Fair-Rite/0431164181/?qs=KmHvPbTOE4SbzMQqE/Okzw==

Here are some guidelines for ferrite core use:

• Put the core as close as possible to the equipment.
• If possible take two or three turns through the core. Up to a point, the suppression effect is proportional to turns² (turns-squared).
• If possible, run power and ground together through the core.
• Before buttoning things back up, secure the heavy core to protect the wires and connectors.  This advice is definitely appropriate for boat radio installations, but perhaps not necessary when in a stable environment.

While evaluating the behavior of the QRP Labs QDX transceiver (my post here:  http://wb6cxc.com/?p=244 ), I put together an old-fashioned mixer / filter to let me make more accurate FSK frequency measurements.  I am using my Time Interval Counter, which counts the cycles of a 100 MHz (10 ns) internal timebase, and calculates the frequency of the input signal using simple math:

Frequency = 1 / Period

This works especially well for lower frequencies, where obtaining precise frequency results with a standard cycle-count counter requires extremely long measurement intervals.  The resolution of a reciprocal counter is a function of the timebase, in this case the 10ns timebase provides eight digits of precision with a one-second count interval (10ns / 1s = 1e-8)

Eight digits is good, but when measuring 10.140 MHz WSPR, with its symbol rate of 1.4648 Hz we need to do better.  With three samples per symbol (about the slowest we can sample it), we only have (10ns/ 0.5s), or about 7.5 digits.  This lets us measure a 10.140 MHz signal to about 1/2 Hz resolution.  This will show us the presence of the modulation, but not much more:

Using an external mixer and VFO to shift the 10 MHz signal down to 100 Hz makes a huge difference in measurement resolution.  With our 1/2 second sample rate we still have 7.5 digits of resolution, but since we a re measuring a 100 Hz signal the resolution is now about 0.00005 Hz!

But I don’t need an external mixer and VFO — all that can be done digitally inside the gate-array I use on my frequency counter:

So I added those to the FPGA logic: 

This is the block diagram of the signal path in the counter.  The blue boxes are contained in the gate-array, and the grey boxes are discrete components on the circuit board.  Not shown are the uController, and a few other sections inside the gate-array.

There are four input stages, configurable for 50-Ohm or High-Z input (compatible with a 10X ‘scope probe), AC or DC coupled.  Each stage, the NCO, the 10 MHz TCXO, and a few other sources (not shown) feed a N-way selector that feeds four divider/timestamp blocks.  The switch also allows any of the input ports to feed a 10 MHz reference clock to the internal 100 MHz PLL.  This allows the counter to use an external OCXO or GPS-disciplined oscillator for increased precision.  In addition, the switch selects the mixer inputs.

The NCO is driven by the 100 MHz clock, and is 29-bits wide.  This provides a frequency resolution of 100 MHz / 2e29, or 0.186xxx Hz, and a maximum frequency of 50 MHz.  The 100 MHz clock means there will be a jitter of 10ns in the NCO frequency.

The NCO or an external signal drives the “clock” of a simple flip-flop mixer, and the external signal feeds the “D” input  This acts as a subtractor.  With perfect input signals there will only be a difference output, there will be no sum as you would see with an analog double-balanced mixer (or with a digital XOR gate).  But we don’t have perfect inputs, as these have been sampled and synchronized by the 100 MHz internal counter clock.  There is plenty of jitter on these mixer inputs, and the output can look like this:

This isn’t a mixer difference frequency, it’s the result of jitter on (relatively) close frequencies.  Here the input is 10.14018 MHz and the NCO is running at 10.1387 MHz, giving a 1.483 KHz difference frequency.  But we can’t count that mess!

So I added a simple digital filter after the mixer.  This is a simple 8-bit up/down counter that limits at 0 and 255.  It’s essentially an integrator, counting up when the input is a “1″ and counting down when the input is “0″.  The output goes high when the count hits 255, and stays high until the count hits 0.  This results in a low-pass filter with a cutoff frequency of (100 MHz / 255) / 2, or 196 KHz.  Here’s that same noisy mixer output after it passes through the filter:

This cleaned-up signal is then fed to one of the divider/timestamp stages and the timestamps are read by the uController, converted to frequency,  and then sent over the counter serial port for logging or further processing.  This serial port can only handle report rates of about 50 per second, so the divider has to be set appropriately.  With a 1KHz mixer output the divider is set to 5 for a 50 Hz sample rate (or set to 100 for a 10 Hz rate.)

Here is a 10.140 MHz WSPR measurement, with the NCO set for a difference frequency of about 100 Hz.  The divider is set to 5, giving a sample rate of about 20 Hz:

And here are some of the actual frequency measurements:

Note that only about seven digits are actually meaningful, but that’s still quite useful.

And unless I decide to do more processing with the local uController, because of the slow serial port update rate this mixer down-conversion method is only useful for fairly low-speed FSK measurements.  Of course this is also useful when making other low-bandwidth measurements, such as clock drift.

And there’s still room left inside the FPGA!  What’s next???