Measuring FSK With a Mixing Reciprocal Counter

While evaluating the behavior of the QRP Labs QDX transceiver (my post here: ), I put together an old-fashioned mixer / filter to let me make more accurate FSK frequency measurements.  I am using my Time Interval Counter, which counts the cycles of a 100 MHz (10 ns) internal timebase, and calculates the frequency of the input signal using simple math:

Frequency = 1 / Period

This works especially well for lower frequencies, where obtaining precise frequency results with a standard cycle-count counter requires extremely long measurement intervals.  The resolution of a reciprocal counter is a function of the timebase, in this case the 10ns timebase provides eight digits of precision with a one-second count interval (10ns / 1s = 1e-8)

Eight digits is good, but when measuring 10.140 MHz WSPR, with its symbol rate of 1.4648 Hz we need to do better.  With three samples per symbol (about the slowest we can sample it), we only have (10ns/ 0.5s), or about 7.5 digits.  This lets us measure a 10.140 MHz signal to about 1/2 Hz resolution.  This will show us the presence of the modulation, but not much more:

Counter direct div2M

Using an external mixer and VFO to shift the 10 MHz signal down to 100 Hz makes a huge difference in measurement resolution.  With our 1/2 second sample rate we still have 7.5 digits of resolution, but since we a re measuring a 100 Hz signal the resolution is now about 0.00005 Hz!


But I don’t need an external mixer and VFO — all that can be done digitally inside the gate-array I use on my frequency counter:



So I added those to the FPGA logic: Timing Path 1


This is the block diagram of the signal path in the counter.  The blue boxes are contained in the gate-array, and the grey boxes are discrete components on the circuit board.  Not shown are the uController, and a few other sections inside the gate-array.

There are four input stages, configurable for 50-Ohm or High-Z input (compatible with a 10X ‘scope probe), AC or DC coupled.  Each stage, the NCO, the 10 MHz TCXO, and a few other sources (not shown) feed a N-way selector that feeds four divider/timestamp blocks.  The switch also allows any of the input ports to feed a 10 MHz reference clock to the internal 100 MHz PLL.  This allows the counter to use an external OCXO or GPS-disciplined oscillator for increased precision.  In addition, the switch selects the mixer inputs.

The NCO is driven by the 100 MHz clock, and is 29-bits wide.  This provides a frequency resolution of 100 MHz / 2e29, or 0.186xxx Hz, and a maximum frequency of 50 MHz.  The 100 MHz clock means there will be a jitter of 10ns in the NCO frequency.

The NCO or an external signal drives the “clock” of a simple flip-flop mixer, and the external signal feeds the “D” input  This acts as a subtractor.  With perfect input signals there will only be a difference output, there will be no sum as you would see with an analog double-balanced mixer (or with a digital XOR gate).  But we don’t have perfect inputs, as these have been sampled and synchronized by the 100 MHz internal counter clock.  There is plenty of jitter on these mixer inputs, and the output can look like this:

TEK0002 TEK0003This isn’t a mixer difference frequency, it’s the result of jitter on (relatively) close frequencies.  Here the input is 10.14018 MHz and the NCO is running at 10.1387 MHz, giving a 1.483 KHz difference frequency.  But we can’t count that mess!

So I added a simple digital filter after the mixer.  This is a simple 8-bit up/down counter that limits at 0 and 255.  It’s essentially an integrator, counting up when the input is a “1″ and counting down when the input is “0″.  The output goes high when the count hits 255, and stays high until the count hits 0.  This results in a low-pass filter with a cutoff frequency of (100 MHz / 255) / 2, or 196 KHz.  Here’s that same noisy mixer output after it passes through the filter:


This cleaned-up signal is then fed to one of the divider/timestamp stages and the timestamps are read by the uController, converted to frequency,  and then sent over the counter serial port for logging or further processing.  This serial port can only handle report rates of about 50 per second, so the divider has to be set appropriately.  With a 1KHz mixer output the divider is set to 5 for a 50 Hz sample rate (or set to 100 for a 10 Hz rate.)

Here is a 10.140 MHz WSPR measurement, with the NCO set for a difference frequency of about 100 Hz.  The divider is set to 5, giving a sample rate of about 20 Hz:

wspr 2And here are some of the actual frequency measurements:

flist 2

Note that only about seven digits are actually meaningful, but that’s still quite useful.

And unless I decide to do more processing with the local uController, because of the slow serial port update rate this mixer down-conversion method is only useful for fairly low-speed FSK measurements.  Of course this is also useful when making other low-bandwidth measurements, such as clock drift.

And there’s still room left inside the FPGA!  What’s next???


DX with the QDX

DXThis morning I was chatting on 40 meters with a local JS8 operator , about 50 miles distant, and was monitoring PSKreporter to see where the little 3W signal from the QDX was showing up.

How about Australia!  I don’t know if this is technically “gray line” propagation, but I am impressed!


QDX Sensitivity Test

I still haven’t done a full evaluation of the QRP Labs QDX transceiver, but I did run a quick check of the receiver performance, comparing it to the Icom IC-7200 (which also has a native  USB interface for audio and CAT control):

ComparisonHere you see two instances of WSJTX, running FT8 on 20 meters.  My off-center-dipole was connected to a coax TEE, feeding both the QDX and the 7200.  No effort was made to match impedances, but since both radios are getting an identical signal that should be good enough for a comparison.  Obviously the transmitters were not activated during this test.

I let the programs run for fifteen minutes and then compared the logfiles.  The7200 logged 524 decodes, while the QDX logged  530.  The Signal/Noise ratio was generally the same, with the QDX showing one or two dB improvement on the stronger signals.  These small differences may be due to the AGC or the slightly narrower filters on the Icom rig.

This test was done if a fairly quiet location, with no nearby strong signals.

Conclusion:  So far, the QDX receiver is a good performer.


Building and Testing the QRP Labs QDX Digital Transceiver

I recently built the QRP Labs QDX transceiver,  which is a remarkable little radio, designed for FSK modes (FT8, JS8, WSPR, etc.)  on the 80-20 meter ham bands.QDX-2This rig has some very clever design inside.  Instead of the standard SSB modulator and demodulator, this uses a USB interface for audio and CAT rig control (emulating a Kenwood TS-440), and measures the audio input tone, using that measured audio frequency and the set “carrier” frequency to program the internal Si5351 clock chip.  This way it directly generates the transmit frequency — no sideband modulator / filter, no linear amplifier, just the synthesizer and an efficient Class-D 5W power amplifier.

On receive, the radio uses a “Tayloe” mixer, using the Si5351 to generate the necessary quadrature clocks.  The I and Q mixer outputs are digitized and processed in a software SSB demodulator.  This digital audio is sent out the USB interface, to a program such as WSJTX.

There’s much worth studying in this design and Hans Summers (the designer) has provided some excellent documentation:

It took me about three hours to build this radio.  The kit comes with all the surface-mount components already loaded, so I only had to solder a handful of capacitors and wind some toroids.


There has been some discussion about the four power transistors — they do run a bit warm and people have burned them out trying for higher power (or due to bad SWR).  I ran the transmitter into a dummy load for about two minutes and measured the transistor temperatures.  This had stabilized at about 50 degrees C:

QDX 2 minutes TX


The signal transmitted by this radio is clean, with harmonics well under the FCC requirements (those close-in spurs may not actually be there.  The spectrum analyzer I was using has some spurious responses of its own):20m 1

After this I gave the radio a spin on 20 meters, using WSJTX running on a small, inexpensive linux box, the Inovato “QUADRA”.  This little computer is comparable to the Raspberry Pi-3, and only costs $30 (power supply and HDMI cable included).  I installed JS8CALL, WSJTX, and Direwolf using the command-line “sudo apt-get install [program name]“, and everything went without a hitch.  Running FT8 for a few minutes resulted in this:



A friend had noted that the QDX wasn’t perfectly generating some of the smaller frequency shifts used in some FSK modes.  Hans has acknowledged the problem and is working on a firmware update, but I decided to look into this.  First I used my “Signalhound USB-SA44B” spectrum analyzer, in the modulation analysis mode.  FT8 looked good:

QDX FT8 mod 1

Note the frequency dither, as the QDX can’t decide on which frequency to send.  This should have absolutely no impact on performance.  8-FSK FT8 uses a tone-spacing of 6.25 Hz.

WSPR was next, and there are issues here.  The 4-FSK WSPR tone spacing is a narrower 1.456 Hz, and the QDX has difficulty generating these evenly-spaced tones.  Here is the analyzer modulation display for 30 meter WSPR:

4FSK Measurement

Notice how the tone frequency steps aren’t even.  Tone 1 should be halfway between tone 0 and tone 2 (and it isn’t).  I wasn’t able to measure exact tone frequencies with the modulation analyzer mode, so I put together a different test setup:



This technique mixes the output of the transmitter with a fixed-frequency signal generator, and the resulting difference frequency can be measured by a frequency counter.  I used a Time Interval Counter of my own design that does “reciprocal” counting where the period of the input signal is measured with 10ns resolution, resulting in fast and accurate measurement, especially for low frequency inputs.  These measurements are sent to a PC where they can be plotted and analyzed.

Modulation Measurement Setup

I had all the pieces lying around except for my low-pass filter, for which I put a simple R-C netwotk (470 Ohms series, 0.1uF shunt) and some SMA connectors on a bit of circuit board.  That Altoids tin contains a simple Si5351 clock generator, a tiny controller, and a not-particularly-stable crystal oscillator.

So here are some measurement results:

Meas Screen

This was done with the mixing generator set about 40 Hz lower than the QDX WSPR transmission.  The counter is pre-dividing the 40Hz difference frequency by four, resulting in a measurement rate of about 10Hz.  This gives about 14 or 15 samples per WSPR symbol.  Here we can see the same problem with the QDX frequency setting — this time it’s Tone 2 that is shifted.  The specifics of the shift or frequency error depends on the actual audio frequency coming in to the QDX (sent my WSJTX).  Here is the modulation with the WSPR transmit offset at 1404Hz (I believe that slow frequency shift is the QDX as it warms up, but I should test that using a better frequency reference):



Note that the step error is at the low-frequency end.  Incrementing the audio frequencies by 1 Hz gives us this with the error at the upper frequency end:


I saw the same error-vs-audio-frequency behavior as when using the spectrum analyzer modulation test.  As another check, I used my drift-buoy controller/synthesizer as a WSPR source (here, generating random WSPR -4FSK tones, and the measurements put into a spreadsheet in order to zero-reference the frequencies):

Counter-BuoyThe tone frequencies are correct.

The QDX  displays this WSPR frequency issue on both 30 and 20 meters,  and I assume on the other bands as well.  I have used the QDX to successfully transmit WSPR, so this amount of error isn’t necessarily critical, but I look forward to enhanced performance in the near future.

For what it’s worth, the Time Interval Counter (TIC) I am using (and designed) is able to directly measure the WSPR modulation at the 10.140… MHz carrier frequency, without using the fancy mixing / down-conversion arrangement:

Counter direct div2M

Here the TIC has pre-divided the MHz input frequency by 2,000,000 which gives us about five measurements per second, about the slowest rate that will reasonably measure 1.456 Hz symbol rate of WSPR.  With the 10 ns resolution of the TIC, this  results in frequency measurements with about 1/2 Hz resolution.  This is good enough to show the modulation, but not good enough to accurately measure it.

The down-conversion method, by directly mixing the MHz signal down to about 100Hz, provides a single-cycle frequency resolution of about 0.0001 Hz.  Since I am measuring four cycles, that gives 0.000025 Hz resolution, certainly enough to accurately measure WSPR deviation!



Version 2 Battery Charger and Boost Regulator


After blowing up the transmitter power amplifier (1W) one too many times during test, I decided that it would be useful to put a current-limit circuit on my Charge/Boost board.  This board takes the power from two 1W solar panels, and uses that to charge the Li-ion battery in a controlled manner.  The battery powers the Drift Buoy and, through a switching boost converter provides 13V to the transmitter amplifier stage.

The Class-E transmitter amplifier is sensitive  to loading, and a badly-matched load can cause excessive power dissipation or over-voltage in the transistors.  In the process of trying to determine the safe limits for the amplifier I’ve managed to smoke a few transistors.

So the new regulator design now includes foldback current-limiting.  I’ve added more test points and several configuration options to this board (not all parts will be stuffed at the same time), allowing for easy experimentation.  The previous board had two layers, but this one uses four.  The additional cost is minimal and this allows for a much nicer layout.

The current-limit won’t protect the Class E amplifier under all circumstances, because the amplifier efficiency is due to the careful phasing of transistor voltage and current.  Different loads (resistive and reactive) will cause both amplitude and phase shifts of the voltage and current at the transistor so even with current-limiting there can be excessive transistor dissipation.  Current limiting will help but I also have a big bag of transistors.  And they’re cheap: about  17 cents each.

I should have test results in a couple of weeks.


SWR Bridge

I finally put the components on the SWR bridge board:

SWR SchematicSWR Bridge Schematic

The SWR bridge uses a common two-transformer directional coupler design, and should have very low excess loss.  Typically the coupled taps are designed for a 50 Ohm impedance, which makes perfect sense if you want to connect it to other test equipment.  But here we are using a full-wave rectifier diode detector design, and we can reduce the loss, or increase the sensitivity, by scaling up the impedance at the coupled ports.  Here I adjusted the transformer turns ratios to drive a 100 Ohm load at the detector ports.

SWR-3D3D KiCad Rendering

 It turns out that there is a downside to how quick/easy/cheap the design-to-PCB process is.  First, I spent some hours simulating various circuit options in LTSpice  Then, using KiCad for schematic capture and circuit-board layout,  I had the schematic and PCB design finished in one evening.  This included building some custom symbols and footprints for my toroid coils and the Schottky diodes I had chosen.  That same evening I sent the PCB files over the internet to JLCPCB, and selecting the next-to-cheapest delivery option I had five boards fabricated and shipped for $12.80.  Complete(!)  These were two-layer boards, but four-layer are only very slightly more expensive.  Since the component count was low, I chose to not get the stainless solder-paste stencil, but those are also quite inexpensive and certainly worth it if you have a more complicated board.

So what’s the downside?  It’s so easy, quick, and cheap that I  perhaps don’t spend enough time checking my work.  Turns out I had four silk screened reference designators swapped (which meant I installed those parts in the wrong location), and I had screwed up the location of two diodes in my original schematic.  Fortunately, all the traces are on the top side, and it was easy to cut traces and solder wires to fix that little SNAFU.

PCBBoard Under Test (with cuts and bodge-wires)

 With those fixes I was able to test the SWR detector with my signal generator at +20 dBm (1/10 W), and using my Drift Buoy amplifier at +30 dBm (1 W).  I was able to test with SWR of 1:1, infinity,  1.27:1, and 1.168 (these last two using a 10dB attenuator with open and shorted outputs).  I’m going to have to do more measurements at different SWRs.  I will be measuring the forward and reverse detector output voltages with the Drift Buoy A/D converter, and since the diodes are non-linear, will need to characterize the behavior at different power levels and SWR values.

loss2Through-Loss (-0.2dB @ 10 MHz)

 The last test was a loss measurement using my spectrum analyzer and tracking generator.  I hadn’t been too concerned about behavior far away from the 10 MHz frequency of operation, but it looks like the SWR bridge behaves well beyond 100 MHz.  The loss at 10 MHz is about 0.2 dB, which is pretty good.

By the way, those white wires on the toroids are the two-turn center-tapped windings.  I used a trace on the PBC for the center-tap connection and use two hairpin wires for the turns.




Battery Charger / Boost Regulator

As mentioned, I still needed to build the Li-Ion battery charger / boost regulator board.


This charger circuit takes the output from two 1W solar panels and uses that power to charge the Li-Ion battery.  The charge-controller is not an MPPT design, just a linear regulator with other features.  But the solar panel output voltage fairly well matches the Li-Ion requirements, so not enough power is wasted to justify using a more complicated circuit.  The charger provides a signal output that indicates the charging current,  and the Buoy controller monitors this and the battery voltage so we should have a good idea of the battery state.

The boost converter input comes from a Li-Ion battery, nominal voltage 3.7V to 4.2V.  The output is 13.4V, nominal load about 100mA (this powers the Buoy 1W 10MHz power amplifier.

So, I collected the components, dabbed solder-paste on the PCB, hand-placed the parts, and put it in my converted toaster-oven reflow oven.  It came out great, but I discovered that I had four resistors mis-identified on the silkscreen. I also was missing a couple of the resistor values so I had to to substitute some that were physically too big.  The completed boards looks good, except where I had to hand-solder to correct my mistakes:

test-2(I need to clean off that scorched flux!)

I hooked it up to some test gear and put the boost converter through its paces.  I measured about 87% efficiency for the converter, and only a few degrees temperature rise for the components:

test-3Thermal Scan

test-1Testing the boards

See that little perfboard with the transistor?  That fixes a problem with my overall design.  The boost-converter chip has an enable pin, and I am planning to use that to get software control of the amplifier power.  Well, the converter shuts down, but even then the Li-Ion battery voltage still sneaks through the converter circuit (through the inductor and diode), applying about 3.5V to the amplifier:

SW1Essential Boost Converter Circuit

I ended up inserting a PMOS FET switch between the converter and the amplifier, which disconnects when the input is under 5V.  It works quite well, and those two LEDS used as low-voltage Zeners, (sort of) gently glow when power is applied (about 0.1 mA through the LEDs):

PGateLow-Voltage Shutoff Circuit

I’m not done with this board yet, I still need to test the solar panel and charger circuit.  I was worried about that boost converter ripple (it switches at about 1MHz) getting into the transmitter output.  I’ve got LC filters on the power input, but is that enough?

Good news: testing shows no detected switching-related spurs above my -80dBc noise floor.


Drift Buoy Preview

The Drift Buoy project is much like sailing is for me:  The destination is quite secondary to the journey.  But in addition to enjoying the scenery along the way, I have also been making progress on actually building the thing.  Here is some evidence:

ControllerThe Buoy Controller

control board 1Buoy Controller Under Test

V0.2-Schematic1W Class-E Power Amplifier

V0.2-3DPower Amplifier

Thermal V2
Power Amplifier Under Test (thermal measurements)

Rev 2 OutputPower Amplifier Output Spectrum (with 30dB attenuator)

I still have two more PC boards waiting for me to build and test; a little power/SWR bridge that will be monitored by the Buoy controller, and a solar panel-input battery charger, combined with a 3.7V -to- 12V boost switching regulator (for the amplifier power supply).

I’m also probably going to hack a wireless NRF24L01 transceiver module onto the controller, giving me the ability to remotely access the controller debug interface (up to about 100 meters distance).  This will not be activated when the buoy is actually at sea, but will let me keep tabs on things when the buoy is floating close to home.

I will be providing details here, covering the more interesting (I hope) aspects of the Buoy.




Fractional (and other) Dividers

Since I am so enthusiastic about the fractional dividers used in the Si5351 (and about fractional dividers in general — in my career I’ve designed these into many telecommunications projects), I thought it appropriate to describe some details.

There are many types of dividers used in frequency synthesis and clock generation.  The basic “divide by N” counter will take an input clock and output a clock at the frequency of (input / N).  N can be any integer.  This works well if you want to generate (say) a 2 MHz clock from a 10 MHz input — just divide by 5.  But if you want to generate a 4 MHz clock, or a 1.875 MHz clock you just can’t get there from here using a plain divide-by-N.

Another divider commonly used in communications design is the Numerically Controlled Oscillator (NCO), which is essentially an adder and an accumulator (register bank).


The adder takes the accumulator output and adds a constant value (the addend “N”), the sum going back into the accumulator.  The accumulator overflows once per output cycle.  If you wanted to generate that 1.875 MHz signal from your 10 MHz clock, you could use a 4-bit NCO, with the addend = 3.  This gives you a division of 16/3, and an output frequency of 1.875 MHz.  With this 4-bit NCO you can get ratios of 1/16, 2/16, 3/16 … 7/16, 8/16.  Interestingly though, you can’t divide by 5, you can only divide by (2^k)/N, where k is the size of the accumulator.  If you increase the size of the NCO you can get arbitrarily close to any desired fraction, and NCOs of 32-bits and larger are common.

The NCO also has the useful feature of providing a parallel output that can be used to drive a sine (or other function) lookup table, which can be used to generate low-distortion, low-jitter signals.  Modern function-generators and radios usually use NCOs for this reason.

But sometimes you just need (or want) to divide precisely by some arbitrary number that isn’t limited to an integer or related to a power of two.  Or, you don’t need the parallel output of the NCO.  This is where the fractional divider (FD) comes in.  There are ways to work around this NCO divisor limitation by dynamically altering the addend, but this complication may not be warranted. The FD has a shorter datapath and uses fewer gates than the NCO, which translates to higher speed, lower power, smaller chip area, and lower cost.  It can fit and operate where NCOs just don’t.

The fractional divider is sometimes called a “clock-dropping” divider.  For example, to divide by 2-1/2 (or 5/2), the FD will divide by 2,3,2,3,2,3…    frac 5,2

To divide by 3-2/3 (or 11/3) the FD divides by 3,4,4,3,4,4…frac 11,3

Dividing by 8-1/2 (or 17/2) gives this output:frac 17,2

You can see that the output signal is “stretched” by one clock-cycle at a regular rate.  This stretching, or dropped-clock, causes jitter, or frequency modulation of the output clock, which may need to be filtered out.  In the “8-1/2″ example above, with a 10 MHz input the output is 10 MHz / (8-1/2), or 1.17647xxx MHz, and the  repeating “8,9,8,9″ pattern  at the output creates a frequency modulation of 1.17647xxx MHz / 2.  The Si5351 uses a delay-line interpolator on the output FD which very effectively cleans up this jitter modulation.  The jitter from the FD used in the Si5351 PLL is attenuated by the PLL loop filter.  In other FD applications this filtering can often be performed by a simple bandpass filter.

For what it’s worth, sometimes with an NCO we want to use only the most-significant bit, and in this case there will also be this type of dropped-clock jitter.  That’s just a fact of life with a purely synchronous design.

Extreme frequency resolution is a powerful feature of the fractional divider.  For example, take the divide value of 8+25/100. This is of course equal to 8.25 .  But change the fraction to 8+32/127 and we get 8.251968xxx.   The fraction 8+31/123 equals 8.252032xxx. Since the Si5351 allows for numerator and denominator values up to 1,048,575 there is the potential for extreme precision.  Look up the “Farey Sequence” for more information on the resolution of fractions.

There are many ways to implement a fractional divider.  Here is a version designed in Verilog, which is a language used to design logic to be synthesized into an FPGA or other ASICs.  This design uses an 8-bit counter, which can generate any ratio  N/D, where (1 < D < 64) and (1 < N < (D / 2)).

module frac(
	input clk,
	input rst,
	input [7:0] b,
	input [7:0] c,
	output reg q
	reg [7:0] sr;

	always @(posedge clk) begin
		if (rst) begin
			sr <= 8'b0; 
			q <= 0;
		else if (sr[7]) begin
			sr <= sr + b;
			q <= ~q;
		else sr = sr - c;

I have based this design on the “Bresenham line-drawing algorithm”, which was originally a very clever way to draw sloping lines on a graphics display without needing to use floating-point math.  This algorithm has proven useful in many other fields, including clock synthesis.

The fractional divider is flexible, simple, fast, and easy.  So the next time you want to divide a clock by pi, just use a 355/113 fractional divider. That gets you to within 8·10−8 .  Or if that’s not good enough, use 833719/265381 for better than eleven digits accuracy.

FSK with the Si5351 Clock Generator (Increasing the Si5351 register update rate)

The Si5351 spec sheets are complicated and confusing, but in the Arduino universe there are many libraries available for the it.  I started out with the Adafruit one, but have modified it to better suit my needs.  Several modifications were required to allow register updates at my 2.4 KHz interrupt rate.  Others were required, or desired, to clean up some other issues.


  • Increase the nominal Arduino I2C rate from 100 KHz to 400 KHz (the Si5351 supports a 400 KHz I2C rate).
  • The Adafruit library uses individual I2C “write single byte” operations, requiring that the I2C bus start, send an address byte, a data byte, and stop per each byte written.  Instead, where possible I use the I2C “burst write” mode which greatly reduces the number of I2C cycles when updating a register bank.
  • When only the PLL “B” numerator is changed, we don’t have to update all the PLL divider registers.  This speeds up the update.

Not particularly speed-related, but the Adafruit library performs a PLL reset when the dividers are updated.  This is not necessary, and creates frequency glitches.  I removed the reset operation when updating divisors.  This also does speed things up a bit.

Not speed-related, but the Adafruit library uses floating-point when calculating the fractional divider register values.  No doubt this is because the Si5351 app note shows the use of the floating-point “floor()” function in the calculation, but this is not required.  When the calculations are performed in the proper order, simple integer math is completely accurate.

Here is the gist of the code I use to update the PLL divider numerator.  Note the use of floor() in the original Adafruit comments (sorry about the line-wrapping):

void setupPLLnumerator(si5351PLL_t pll, uint8_t a, uint32_t b, uint32_t c) {
  uint32_t P1; /* PLL config register P1 */
  uint32_t P2; /* PLL config register P2 */
  uint32_t P3; /* PLL config register P3 */

  /* Feedback Multisynth Divider Equation
   * where: a = mult, b = num and c = denom
   * P1 register is an 18-bit value using following formula:
   * 	P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512
   * P2 register is a 20-bit value using the following formula:
   * 	P2[19:0] = 128 * num - denom * floor(128*(num/denom))
   * P3 register is a 20-bit value using the following formula:
   * 	P3[19:0] = denom

   uint32_t f;
f   = (128 * b) / c;

    // build the registers to write
    P1 = 128 * a + f - 512;
    P2 = 128 * b - f * c;
    P3 = c;

	// since c (denom) hasn't changed, there's no need to write first two bytes// bytes to be written = 6
    uint8_t reg_bank[] = { 
      //(P3 & 0xFF00) >> 8,          // Bits [15:8] of MSNx_P3 in register 26
      //P3 & 0xFF,
      (P1 & 0x030000L) >> 16,
      (P1 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P1 in register 29
      P1 & 0xFF,                   // Bits [7:0]  of MSNx_P1 in register 30
      ((P3 & 0x0F0000L) >> 12) | ((P2 & 0x0F0000) >> 16), // Parts of MSNx_P3 and MSNx_P1
      (P2 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P2 in register 32
      P2 & 0xFF                    // Bits [7:0]  of MSNx_P2 in register 33

  /* Get the appropriate starting point for the PLL registers */
  uint8_t baseaddr = (26); // PLLA
  i2cWriteBurst(baseaddr + 2, reg_bank, sizeof(reg_bank));

The timer-tick ISR runs at 2.4 KHz (416.66us). With these changes to the Si5351 library code, updating the PLL numerator takes 241us. The long Gaussian filter takes 50us per cycle, and the other operations in the ISR take less than 5us, so that leaves about 120us (per 2.4 KHz cycle) free for other program activities.  This is comfortably adequate, but trying to run the ISR at a faster rate might prove difficult.

For more information on using the Si5351 quadrature mode in radio applications, see this excellent posting by Hans Summers (QRP Labs):

Here is an alternate Si5351 programming library.  I was inspired to improve my I2C functions after looking at this one: